About the Internship
During my internship at Semiconductor Laboratory (SCL) in the Advanced VLSI Design Division, I was tasked with designing and developing a Low Noise Amplifier (LNA) for navigation applications. This project was a comprehensive experience, where I oversaw the entire design process, from initial design and simulations to layout generation and extensive corner analysis.
Working with state-of-the-art tools like Cadence software, I gained valuable insights into RF IC design, testing, packaging, and virtual fabrication. This hands-on experience allowed me to deeply explore both digital and analog IC design, and further solidified my expertise in VLSI design.
Key Highlights
- Full Project Lifecycle: From conceptual design and simulations to post-layout analysis, I led the entire process of creating the LNA.
- EM Simulations: Conducted electromagnetic simulations to ensure the robustness and reliability of the LNA design.
- Mentorship: Worked under the guidance of scientist Rajiv Bhatia, gaining critical insights into VLSI design and Cadence tools.
- Exposure to Semiconductor Facilities: Gained hands-on experience in a semiconductor foundry, enhancing my understanding of IC fabrication and testing.
Technologies Used
- Cadence Software: Used for designing, simulating, and analyzing VLSI circuits.
- RF IC Design: Expertise in designing Low Noise Amplifiers for high-frequency applications.
- EM Simulation Tools: Ensured design performance through Electromagnetic simulations.
Project Report
To explore more about my project, you can view my project report here.
Video Summary
Watch the video summary of my internship experience here.
Networking and Discussions
Feel free to connect with me for any insights or discussions on semiconductor technology and VLSI design. I'm always open to networking and learning from fellow professionals in the field.
